It is often beneficial to be able to examine the microscopic electronic circuitry that is formed on a semiconductor wafer or more accurately, on an individual die such is commonly encapsulated or packaged in a “chip”. Such examination may be required during the development of a new integrated circuit, for controlling quality during the manufacturing process, for failure analysis or for reverse engineering purposes.
Multiple layers of electronic circuitry are formed on the frontside of a semiconductor wafer by a series of processes that are well known in the art. Each wafer includes an array of individual integrated circuits that subsequently separated from one another wherein the wafer is sliced into individual dice so that each includes one such circuit. A plurality of leads are then attached to each die after which such assembly is packaged or encapsulated in a protective case to complete an IC chip. The circuitry that is formed on each individual die includes a plurality of circuit layers that are built up on top of one another. The size of such dice range from about 0.5 mm to about 40 mm on a side, while the thickness ranges from about 0.1 mm to 0.8 mm wherein the thickness of each layer of circuitry is on the order of 1 um.
In order to examine a particular layer of circuitry, the die is “deprocessed” by mechanically or chemo-mechanically polishing its frontside to remove the layers of circuitry that are in place above the layer that is of interest. Polishing is accomplished by causing the face of the die to contact a rotating and oscillating polishing surface or lap. The pressure with which the die is urged against the lap, the softness of the lap, the speed of rotation and oscillation of the lap and the properties of the polishing media are some of the factors that determine the rate at which the die is delayered. Controlling the length of time such delayering process is applied in turn determines the depth of material that is removed. It is of course essential that the frontside face of the die is held parallel to the face of the lap so that the plane defined by the material being removed is parallel to the plane defined by each layer of circuitry. Such parallelism ensures that each successive layer of circuitry becomes exposed in its entirety rather than merely a diagonal slice thereof. The sample may be microscopically examined from time to time during the delayering process to monitor the progress that is being made both in terms of the depth of material that has been removed as well as whether parallelism is being maintained so that the appropriate adjustments can be made.
An approach that has heretofore been relied upon to delayer a die includes use of a fixture to positively maintain the orientation of a workpiece constant while such fixture is moved or floats in the Z direction so as to urge the die against a polishing surface that is rotating and oscillating on the X-Y plane. The die is attached to a flat surface which is tilt adjustable relative to the fixture and hence the polishing surface. Alignment of the die relative to the polishing surface is achieved by measuring the distance from various points on the frontside face of the die to a reference surface with the use of a dial indicator. A number of disadvantages are inherent in such an approach. Firstly, the accuracy of a dial indicator is limited and may not be able to repeatably discern a deviation on the order of a micron across the face of a die. Secondly, the physical contact between the dial indicator and the die that is necessary may disturb or distort the die surface and may thereby adversely affect the accuracy of the measurement. Finally, the die and its fixture must be lifted off of the surface of the lap or even detached from the associated support in order to afford access to the frontside surface of the die to allow the measurements to be made. Replacement of the fixture and reengagement of the lap surface by the die may introduce errors that adversely effect the die's orientation, i.e. its parallelism relative to the polishing surface.
An improved approach is needed that allows a die's frontside surface to be quickly, easily and accurately aligned with a polishing surface. Furthermore, it is highly desirable that the die's parallelism can be adjusted and checked while the polishing surface is engaged so as to eliminate errors that may be introduced in shifting, removing or otherwise manipulating the die and its fixture for the purpose of measuring its alignment. Finally, it is similarly highly desirable for the measurement to be taken without physically engaging the surface of the frontside of the die so as to eliminate any possibility of disturbing the circuitry on the surface of the die and possibly also adversely affecting the accuracy of the measurement.